Arto's Notes re: RISC-V


Development Boards




  • User-Level ISA
  • Privileged ISA
  • Compressed Instructions


  • Three base integer ISAs, one per address width
    • RV32I, RV64I, RV128I.
    • Only 40 hardware instructions needed to run Linux.
  • Fairly standard fixed 32-bit RISC instruction encoding.

Standard Extensions

  • M: Integer multiply/divide.
  • A: Atomic memory operations. (AMOs + LR/SC)
  • F: Single-precision floating point.
  • D: Double-precision floating point.
  • G: "General-purpose" ISA. (IMAFD)
  • Q: Quad-precision floating point.

Miscellaneous Extensions

  • C: Compressed Instruction Extension.

Base ISA Details

  • 32-bit fixed-width, naturally aligned instructions.
  • 31 integer registers (x1-x31), plus x0 zero register.
  • No implicit registers, rs1/rs2/rd in fixed location.
  • Floating-point adds 32 FP registers (f0-f31) plus FP CSR, also fused multiply-add four-register format.
  • Designed to support PIC and dynamic linking.

Instruction Formats

  • R-type
  • I-type
  • S-type
  • U-type

See Also

  • Arto's Notes re: lowRISC, an open-source SoC based on RISC-V